Timing Report

Need help reading this report?

Design Name sw2_pld_main
Device, Speed (SpeedFile Version) XCR3512XL, -12 (6.0)
Date Created Mon Jun 12 16:13:51 2006
Created By Timing Report Generator: version H.42
Copyright Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.
Possible asynchronous logic: Clock pin 'FB22__ctinst/5' has multiple original clock nets 'demux_dsp_sel_tri<1>_MC.Q' 'demux_dsp_sel_tri<3>_MC.Q' 'demux_dsp_sel_tri<2>_MC.Q' 'demux_dsp_sel_tri<0>_MC.Q'.
Possible asynchronous logic: Clock pin 'FB26__ctinst/4' has multiple original clock nets 'demux_dsp_sel_load<1>_MC.Q' 'demux_dsp_sel_load<3>_MC.Q' 'demux_dsp_sel_load<2>_MC.Q' 'demux_dsp_sel_load<0>_MC.Q'.
Possible asynchronous logic: Clock pin 'FB22__ctinst/4' has multiple original clock nets 'demux_chip_sel_tri<1>_MC.Q' 'demux_chip_sel_tri<3>_MC.Q' 'demux_chip_sel_tri<2>_MC.Q' 'demux_chip_sel_tri<0>_MC.Q'.

Performance Summary
Min. Clock Period 53.400 ns.
Max. Clock Frequency (fSYSTEM) 18.727 MHz.
Limited by Cycle Time for CLK
Clock to Setup (tCYC) 53.400 ns.
Pad to Pad Delay (tPD) 12.800 ns.
Setup to Clock at the Pad (tSU) 48.300 ns.
Clock Pad to Output Pad Delay (tCO) 38.900 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
TS1002 0.0 0.0 0 0
TS1003 0.0 0.0 0 0
TS1004 0.0 0.0 0 0
TS1005 0.0 0.0 0 0
TS1006 0.0 0.0 0 0
TS1007 0.0 0.0 0 0
TS1008 0.0 0.0 0 0
TS1009 0.0 0.0 0 0
TS1010 0.0 0.0 0 0
TS1011 0.0 0.0 0 0
TS1012 0.0 0.0 0 0
TS1013 0.0 0.0 0 0
TS1014 0.0 0.0 0 0
TS1015 0.0 0.0 0 0
AUTO_TS_F2F 0.0 53.4 3059 3059
AUTO_TS_P2P 0.0 38.9 83 83
AUTO_TS_P2F 0.0 27.4 402 402
AUTO_TS_F2P 0.0 27.6 214 214


Constraint: TS1000

Description: PERIOD:PERIOD_sample_reg_load_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_status_reg_load_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1002

Description: PERIOD:PERIOD_demux_dsp_sel_tri<1>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1003

Description: PERIOD:PERIOD_demux_dsp_sel_tri<3>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1004

Description: PERIOD:PERIOD_demux_dsp_sel_tri<2>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1005

Description: PERIOD:PERIOD_demux_dsp_sel_tri<0>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1006

Description: PERIOD:PERIOD_demux_dsp_sel_load<1>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1007

Description: PERIOD:PERIOD_demux_dsp_sel_load<3>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1008

Description: PERIOD:PERIOD_demux_dsp_sel_load<2>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1009

Description: PERIOD:PERIOD_demux_dsp_sel_load<0>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1010

Description: PERIOD:PERIOD_status_reg_load_out_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1011

Description: PERIOD:PERIOD_demux_chip_sel_tri<1>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1012

Description: PERIOD:PERIOD_demux_chip_sel_tri<3>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1013

Description: PERIOD:PERIOD_demux_chip_sel_tri<2>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1014

Description: PERIOD:PERIOD_demux_chip_sel_tri<0>_MC.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1015

Description: PERIOD:PERIOD_CLK:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
demux_chip_sel_tri<0>.Q to FSM/SHELL1_DSP_SM_2/cntr_rst.D 0.000 53.400 -53.400
demux_chip_sel_tri<0>.Q to status_reg_data<0>.D 0.000 53.400 -53.400
demux_chip_sel_tri<0>.Q to status_reg_data<2>.D 0.000 53.400 -53.400


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
CLK to dsp_data<0> 0.000 38.900 -38.900
CLK to dsp_data<1> 0.000 38.900 -38.900
CLK to dsp_data<2> 0.000 38.900 -38.900


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
dsp_add<0> to FSM/SHELL1_DSP_SM_2/tochip_command1.D 0.000 27.400 -27.400
dsp_add<1> to FSM/SHELL1_DSP_SM_2/tochip_command1.D 0.000 27.400 -27.400
dsp_add<2> to FSM/SHELL1_DSP_SM_2/tochip_command1.D 0.000 27.400 -27.400


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
demux_dsp_sel_tri<0>.Q to dsp_data<0> 0.000 27.600 -27.600
demux_dsp_sel_tri<0>.Q to dsp_data<1> 0.000 27.600 -27.600
demux_dsp_sel_tri<0>.Q to dsp_data<2> 0.000 27.600 -27.600



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
sample_reg_load_MC.Q 100.000 Limited by Clock Pulse Width for sample_reg_load_MC.Q
status_reg_load_MC.Q 100.000 Limited by Clock Pulse Width for status_reg_load_MC.Q
demux_dsp_sel_tri<1>_MC.Q 100.000 Limited by Clock Pulse Width for demux_dsp_sel_tri<1>_MC.Q
demux_dsp_sel_tri<3>_MC.Q 100.000 Limited by Clock Pulse Width for demux_dsp_sel_tri<3>_MC.Q
demux_dsp_sel_tri<2>_MC.Q 100.000 Limited by Clock Pulse Width for demux_dsp_sel_tri<2>_MC.Q
demux_dsp_sel_tri<0>_MC.Q 100.000 Limited by Clock Pulse Width for demux_dsp_sel_tri<0>_MC.Q
demux_dsp_sel_load<1>_MC.Q 100.000 Limited by Clock Pulse Width for demux_dsp_sel_load<1>_MC.Q
demux_dsp_sel_load<3>_MC.Q 100.000 Limited by Clock Pulse Width for demux_dsp_sel_load<3>_MC.Q
demux_dsp_sel_load<2>_MC.Q 100.000 Limited by Clock Pulse Width for demux_dsp_sel_load<2>_MC.Q
demux_dsp_sel_load<0>_MC.Q 100.000 Limited by Clock Pulse Width for demux_dsp_sel_load<0>_MC.Q
status_reg_load_out_MC.Q 100.000 Limited by Clock Pulse Width for status_reg_load_out_MC.Q
demux_chip_sel_tri<1>_MC.Q 100.000 Limited by Clock Pulse Width for demux_chip_sel_tri<1>_MC.Q
demux_chip_sel_tri<3>_MC.Q 100.000 Limited by Clock Pulse Width for demux_chip_sel_tri<3>_MC.Q
demux_chip_sel_tri<2>_MC.Q 100.000 Limited by Clock Pulse Width for demux_chip_sel_tri<2>_MC.Q
demux_chip_sel_tri<0>_MC.Q 100.000 Limited by Clock Pulse Width for demux_chip_sel_tri<0>_MC.Q
CLK 18.727 Limited by Cycle Time for CLK

Setup/Hold Times for Clocks

Setup/Hold Times for Clock sample_reg_load.Q
Source Pad Setup to clk (edge) Hold to clk (edge)
data<10> -7.400 8.100
data<11> -7.400 8.100
data<12> -7.400 8.100
data<13> -7.400 8.100
data<14> -7.400 8.100
data<15> -7.400 8.100
data<16> -7.400 8.100
data<17> -7.400 8.100
data<18> -7.400 8.100
data<19> -7.400 8.100
data<20> -7.400 8.100
data<21> -7.400 8.100
data<22> -7.400 8.100
data<23> -7.400 8.100
data<24> -7.400 8.100
data<25> -7.400 8.100
data<26> -7.400 8.100
data<27> -7.400 8.100
data<28> -7.400 8.100
data<29> -7.400 8.100
data<30> -7.400 8.100
data<31> -7.400 8.100
data<8> -7.400 8.100
data<9> -7.400 8.100

Setup/Hold Times for Clock status_reg_load_out.Q
Source Pad Setup to clk (edge) Hold to clk (edge)
dsp_data<0> -2.400 3.100
dsp_data<1> -2.400 3.100
dsp_data<2> -2.400 3.100
dsp_data<3> -2.400 3.100
dsp_data<4> -5.300 6.000
dsp_data<5> -5.300 6.000
dsp_data<6> -5.300 6.000
dsp_data<7> -5.300 6.000

Setup/Hold Times for Clock CLK
Source Pad Setup to clk (edge) Hold to clk (edge)
dsp_add<0> 25.900 0.000
dsp_add<1> 25.900 0.000
dsp_add<2> 25.900 0.000
dsp_add<3> 25.900 0.000
dsp_are_l 16.900 0.000
dsp_asm2_l 16.900 0.000
dsp_awe_l 16.900 0.000
dsp_data<0> 48.300 0.000
dsp_data<10> 16.900 0.000
dsp_data<11> 16.900 0.000
dsp_data<12> 16.900 0.000
dsp_data<13> 16.900 0.000
dsp_data<14> 16.900 0.000
dsp_data<15> 16.900 0.000
dsp_data<16> 16.900 0.000
dsp_data<17> 16.900 0.000
dsp_data<18> 16.900 0.000
dsp_data<19> 16.900 0.000
dsp_data<1> 48.300 0.000
dsp_data<20> 16.900 0.000
dsp_data<21> 16.900 0.000
dsp_data<22> 16.900 0.000
dsp_data<23> 25.900 0.000
dsp_data<24> 25.900 0.000
dsp_data<25> 25.900 0.000
dsp_data<26> 16.900 0.000
dsp_data<27> 16.900 0.000
dsp_data<28> 16.900 0.000
dsp_data<29> 16.900 0.000
dsp_data<2> 48.300 0.000
dsp_data<30> 25.900 0.000
dsp_data<31> 16.900 0.000
dsp_data<3> 48.300 0.000
dsp_data<4> 46.600 0.000
dsp_data<5> 46.600 0.000
dsp_data<6> 46.600 0.000
dsp_data<7> 46.600 0.000
dsp_data<8> 16.900 0.000
dsp_data<9> 16.900 0.000


Clock to Pad Timing

Clock CLK to Pad
Destination Pad Clock (edge) to Pad
dsp_data<0> 38.900
dsp_data<1> 38.900
dsp_data<2> 38.900
dsp_data<3> 38.900
dsp_data<4> 38.900
dsp_data<5> 38.900
dsp_data<6> 38.900
dsp_data<7> 38.900
status_reg_load_out 27.700
data<0> 26.100
data<10> 26.100
data<11> 26.100
data<13> 26.100
data<14> 26.100
data<15> 26.100
data<16> 26.100
data<17> 26.100
data<18> 26.100
data<19> 26.100
data<1> 26.100
data<21> 26.100
data<22> 26.100
data<23> 26.100
data<24> 26.100
data<25> 26.100
data<26> 26.100
data<27> 26.100
data<29> 26.100
data<30> 26.100
data<31> 26.100
data<12> 24.900
data<20> 24.900
data<28> 24.900
data<2> 23.100
data<3> 23.100
data<4> 23.100
data<5> 23.100
data<6> 23.100
data<7> 23.100
data<8> 23.100
data<9> 23.100
dsp_data<10> 22.500
dsp_data<11> 22.500
dsp_data<12> 22.500
dsp_data<13> 22.500
dsp_data<14> 22.500
dsp_data<15> 22.500
dsp_data<16> 22.500
dsp_data<17> 22.500
dsp_data<18> 22.500
dsp_data<19> 22.500
dsp_data<20> 22.500
dsp_data<21> 22.500
dsp_data<22> 22.500
dsp_data<23> 22.500
dsp_data<24> 22.500
dsp_data<25> 22.500
dsp_data<26> 22.500
dsp_data<27> 22.500
dsp_data<28> 22.500
dsp_data<29> 22.500
dsp_data<30> 22.500
dsp_data<31> 22.500
dsp_data<8> 22.500
dsp_data<9> 22.500
SAN 21.400
col_clk 21.400
pre_sleep 21.400
row_clk 21.400
row_pulse 21.400
sel_clk 21.400
sel_pulse 21.400
PRE 6.900
SH_samp_0 6.900
chip_sel<1> 6.900
cntr_8 6.900
cntr_9 6.900
col_pulse 6.900
comp_sleep 6.900
dac_en 6.900
post_sleep 6.900
transmit 6.900


Clock to Setup Times for Clocks

Clock to Setup for clock CLK
Source Destination Delay
demux_chip_sel_tri<0>.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 53.400
demux_chip_sel_tri<0>.Q status_reg_data<0>.D 53.400
demux_chip_sel_tri<0>.Q status_reg_data<2>.D 53.400
demux_chip_sel_tri<0>.Q status_reg_data<3>.D 53.400
demux_chip_sel_tri<1>.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 53.400
demux_chip_sel_tri<1>.Q status_reg_data<0>.D 53.400
demux_chip_sel_tri<1>.Q status_reg_data<2>.D 53.400
demux_chip_sel_tri<1>.Q status_reg_data<3>.D 53.400
demux_chip_sel_tri<2>.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 53.400
demux_chip_sel_tri<2>.Q status_reg_data<0>.D 53.400
demux_chip_sel_tri<2>.Q status_reg_data<2>.D 53.400
demux_chip_sel_tri<2>.Q status_reg_data<3>.D 53.400
demux_chip_sel_tri<3>.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 53.400
demux_chip_sel_tri<3>.Q status_reg_data<0>.D 53.400
demux_chip_sel_tri<3>.Q status_reg_data<2>.D 53.400
demux_chip_sel_tri<3>.Q status_reg_data<3>.D 53.400
demux_chip_sel_tri<0>.Q transmit.D 52.200
demux_chip_sel_tri<1>.Q transmit.D 52.200
demux_chip_sel_tri<2>.Q transmit.D 52.200
demux_chip_sel_tri<3>.Q transmit.D 52.200
demux_chip_sel_tri<0>.Q demux_chip_sel_tri<0>.D 44.400
demux_chip_sel_tri<0>.Q demux_chip_sel_tri<1>.D 44.400
demux_chip_sel_tri<0>.Q demux_chip_sel_tri<2>.D 44.400
demux_chip_sel_tri<1>.Q demux_chip_sel_tri<0>.D 44.400
demux_chip_sel_tri<1>.Q demux_chip_sel_tri<1>.D 44.400
demux_chip_sel_tri<1>.Q demux_chip_sel_tri<2>.D 44.400
demux_chip_sel_tri<2>.Q demux_chip_sel_tri<0>.D 44.400
demux_chip_sel_tri<2>.Q demux_chip_sel_tri<1>.D 44.400
demux_chip_sel_tri<2>.Q demux_chip_sel_tri<2>.D 44.400
demux_chip_sel_tri<3>.Q demux_chip_sel_tri<0>.D 44.400
demux_chip_sel_tri<3>.Q demux_chip_sel_tri<1>.D 44.400
demux_chip_sel_tri<3>.Q demux_chip_sel_tri<2>.D 44.400
FSM/SHELL1_DSP_SM_2/ramp_cnt0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 43.600
FSM/SHELL1_DSP_SM_2/ramp_cnt0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 43.600
FSM/SHELL1_DSP_SM_2/ramp_cnt1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 43.600
FSM/SHELL1_DSP_SM_2/ramp_cnt1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 43.600
FSM/SHELL1_DSP_SM_2/ramp_cnt2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 43.600
FSM/SHELL1_DSP_SM_2/ramp_cnt2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 43.600
FSM/SHELL1_DSP_SM_2/ramp_cnt3.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 43.600
FSM/SHELL1_DSP_SM_2/ramp_cnt3.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 43.600
demux_chip_sel_tri<0>.Q SH_samp_0.D 43.200
demux_chip_sel_tri<0>.Q demux_chip_sel_tri<3>.D 43.200
demux_chip_sel_tri<0>.Q status_reg_data<1>.D 43.200
demux_chip_sel_tri<0>.Q status_reg_load.D 43.200
demux_chip_sel_tri<1>.Q SH_samp_0.D 43.200
demux_chip_sel_tri<1>.Q demux_chip_sel_tri<3>.D 43.200
demux_chip_sel_tri<1>.Q status_reg_data<1>.D 43.200
demux_chip_sel_tri<1>.Q status_reg_load.D 43.200
demux_chip_sel_tri<2>.Q SH_samp_0.D 43.200
demux_chip_sel_tri<2>.Q demux_chip_sel_tri<3>.D 43.200
demux_chip_sel_tri<2>.Q status_reg_data<1>.D 43.200
demux_chip_sel_tri<2>.Q status_reg_load.D 43.200
demux_chip_sel_tri<3>.Q SH_samp_0.D 43.200
demux_chip_sel_tri<3>.Q demux_chip_sel_tri<3>.D 43.200
demux_chip_sel_tri<3>.Q status_reg_data<1>.D 43.200
demux_chip_sel_tri<3>.Q status_reg_load.D 43.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q status_reg_data<0>.D 42.400
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q status_reg_data<2>.D 42.400
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q status_reg_data<3>.D 42.400
FSM/SHELL1_DSP_SM_2/ramp_cnt4.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 42.400
FSM/SHELL1_DSP_SM_2/ramp_cnt4.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 42.400
FSM/SHELL1_DSP_SM_2/row_cnt0.Q status_reg_data<0>.D 42.400
FSM/SHELL1_DSP_SM_2/row_cnt0.Q status_reg_data<2>.D 42.400
FSM/SHELL1_DSP_SM_2/row_cnt0.Q status_reg_data<3>.D 42.400
FSM/SHELL1_DSP_SM_2/row_cnt1.Q status_reg_data<0>.D 42.400
FSM/SHELL1_DSP_SM_2/row_cnt1.Q status_reg_data<2>.D 42.400
FSM/SHELL1_DSP_SM_2/row_cnt1.Q status_reg_data<3>.D 42.400
FSM/SHELL1_DSP_SM_2/row_cnt2.Q status_reg_data<0>.D 42.400
FSM/SHELL1_DSP_SM_2/row_cnt2.Q status_reg_data<2>.D 42.400
FSM/SHELL1_DSP_SM_2/row_cnt2.Q status_reg_data<3>.D 42.400
FSM/SHELL1_DSP_SM_2/row_cnt3.Q status_reg_data<0>.D 42.400
FSM/SHELL1_DSP_SM_2/row_cnt3.Q status_reg_data<2>.D 42.400
FSM/SHELL1_DSP_SM_2/row_cnt3.Q status_reg_data<3>.D 42.400
cntr_cnt<0>.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 42.400
cntr_cnt<0>.Q status_reg_data<0>.D 42.400
cntr_cnt<0>.Q status_reg_data<2>.D 42.400
cntr_cnt<0>.Q status_reg_data<3>.D 42.400
cntr_cnt<1>.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 42.400
cntr_cnt<1>.Q status_reg_data<0>.D 42.400
cntr_cnt<1>.Q status_reg_data<2>.D 42.400
cntr_cnt<1>.Q status_reg_data<3>.D 42.400
cntr_cnt<2>.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 42.400
cntr_cnt<2>.Q status_reg_data<0>.D 42.400
cntr_cnt<2>.Q status_reg_data<2>.D 42.400
cntr_cnt<2>.Q status_reg_data<3>.D 42.400
cntr_cnt<3>.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 42.400
cntr_cnt<3>.Q status_reg_data<0>.D 42.400
cntr_cnt<3>.Q status_reg_data<2>.D 42.400
cntr_cnt<3>.Q status_reg_data<3>.D 42.400
cntr_cnt<4>.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 42.400
cntr_cnt<4>.Q status_reg_data<0>.D 42.400
cntr_cnt<4>.Q status_reg_data<2>.D 42.400
cntr_cnt<4>.Q status_reg_data<3>.D 42.400
cntr_cnt<5>.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 42.400
cntr_cnt<5>.Q status_reg_data<0>.D 42.400
cntr_cnt<5>.Q status_reg_data<2>.D 42.400
cntr_cnt<5>.Q status_reg_data<3>.D 42.400
cntr_cnt<6>.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 42.400
cntr_cnt<6>.Q status_reg_data<0>.D 42.400
cntr_cnt<6>.Q status_reg_data<2>.D 42.400
cntr_cnt<6>.Q status_reg_data<3>.D 42.400
cntr_cnt<7>.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 42.400
cntr_cnt<7>.Q status_reg_data<0>.D 42.400
cntr_cnt<7>.Q status_reg_data<2>.D 42.400
cntr_cnt<7>.Q status_reg_data<3>.D 42.400
demux_chip_sel_tri<0>.Q FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.D 42.000
demux_chip_sel_tri<1>.Q FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.D 42.000
demux_chip_sel_tri<2>.Q FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.D 42.000
demux_chip_sel_tri<3>.Q FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.D 42.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q row_clk_BUFR.D 41.200
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 41.200
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 41.200
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 41.200
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 41.200
FSM/SHELL1_DSP_SM_2/ramps0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 41.200
FSM/SHELL1_DSP_SM_2/ramps0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 41.200
FSM/SHELL1_DSP_SM_2/ramps0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 41.200
FSM/SHELL1_DSP_SM_2/ramps0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 41.200
FSM/SHELL1_DSP_SM_2/ramps1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 41.200
FSM/SHELL1_DSP_SM_2/ramps1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 41.200
FSM/SHELL1_DSP_SM_2/ramps1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 41.200
FSM/SHELL1_DSP_SM_2/ramps1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 41.200
FSM/SHELL1_DSP_SM_2/row_cnt0.Q row_clk_BUFR.D 41.200
FSM/SHELL1_DSP_SM_2/row_cnt1.Q row_clk_BUFR.D 41.200
FSM/SHELL1_DSP_SM_2/row_cnt2.Q row_clk_BUFR.D 41.200
FSM/SHELL1_DSP_SM_2/row_cnt3.Q row_clk_BUFR.D 41.200
cntr_cnt<0>.Q transmit.D 41.200
cntr_cnt<1>.Q transmit.D 41.200
cntr_cnt<2>.Q transmit.D 41.200
cntr_cnt<3>.Q transmit.D 41.200
cntr_cnt<4>.Q transmit.D 41.200
cntr_cnt<5>.Q transmit.D 41.200
cntr_cnt<6>.Q transmit.D 41.200
cntr_cnt<7>.Q transmit.D 41.200
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 40.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 40.000
FSM/SHELL1_DSP_SM_2/ramps0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 40.000
FSM/SHELL1_DSP_SM_2/ramps0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 40.000
FSM/SHELL1_DSP_SM_2/ramps1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 40.000
FSM/SHELL1_DSP_SM_2/ramps1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 40.000
demux_chip_sel_tri<0>.Q FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.D 34.200
demux_chip_sel_tri<1>.Q FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.D 34.200
demux_chip_sel_tri<2>.Q FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.D 34.200
demux_chip_sel_tri<3>.Q FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.D 34.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q status_reg_data<0>.D 33.400
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q status_reg_data<2>.D 33.400
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q PRE.D 33.400
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q status_reg_load.D 33.400
FSM/SHELL1_DSP_SM_2/CLR_2.Q status_reg_data<0>.D 33.400
FSM/SHELL1_DSP_SM_2/CLR_2.Q status_reg_data<2>.D 33.400
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q status_reg_data<0>.D 33.400
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q status_reg_data<3>.D 33.400
FSM/SHELL1_DSP_SM_2/col_cnt0.Q status_reg_data<0>.D 33.400
FSM/SHELL1_DSP_SM_2/col_cnt0.Q status_reg_data<2>.D 33.400
FSM/SHELL1_DSP_SM_2/col_cnt1.Q status_reg_data<0>.D 33.400
FSM/SHELL1_DSP_SM_2/col_cnt1.Q status_reg_data<2>.D 33.400
FSM/SHELL1_DSP_SM_2/col_cnt2.Q status_reg_data<0>.D 33.400
FSM/SHELL1_DSP_SM_2/col_cnt2.Q status_reg_data<2>.D 33.400
FSM/SHELL1_DSP_SM_2/col_cnt3.Q status_reg_data<0>.D 33.400
FSM/SHELL1_DSP_SM_2/col_cnt3.Q status_reg_data<2>.D 33.400
FSM/SHELL1_DSP_SM_2/col_cnt4.Q status_reg_data<0>.D 33.400
FSM/SHELL1_DSP_SM_2/col_cnt4.Q status_reg_data<2>.D 33.400
FSM/SHELL1_DSP_SM_2/col_cnt5.Q status_reg_data<0>.D 33.400
FSM/SHELL1_DSP_SM_2/col_cnt5.Q status_reg_data<2>.D 33.400
FSM/SHELL1_DSP_SM_2/ramp_cnt0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 33.400
FSM/SHELL1_DSP_SM_2/ramp_cnt1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 33.400
FSM/SHELL1_DSP_SM_2/ramp_cnt2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 33.400
FSM/SHELL1_DSP_SM_2/ramp_cnt3.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 33.400
FSM/SHELL1_DSP_SM_2/ramps0.Q status_reg_data<0>.D 33.400
FSM/SHELL1_DSP_SM_2/ramps0.Q status_reg_data<3>.D 33.400
FSM/SHELL1_DSP_SM_2/ramps1.Q status_reg_data<0>.D 33.400
FSM/SHELL1_DSP_SM_2/ramps1.Q status_reg_data<3>.D 33.400
FSM/SHELL1_DSP_SM_2/row_cnt0.Q PRE.D 33.400
FSM/SHELL1_DSP_SM_2/row_cnt0.Q status_reg_load.D 33.400
FSM/SHELL1_DSP_SM_2/row_cnt1.Q PRE.D 33.400
FSM/SHELL1_DSP_SM_2/row_cnt1.Q status_reg_load.D 33.400
FSM/SHELL1_DSP_SM_2/row_cnt2.Q PRE.D 33.400
FSM/SHELL1_DSP_SM_2/row_cnt2.Q status_reg_load.D 33.400
FSM/SHELL1_DSP_SM_2/row_cnt3.Q PRE.D 33.400
FSM/SHELL1_DSP_SM_2/row_cnt3.Q status_reg_load.D 33.400
cntr_cnt<0>.Q demux_chip_sel_tri<0>.D 33.400
cntr_cnt<0>.Q demux_chip_sel_tri<1>.D 33.400
cntr_cnt<0>.Q demux_chip_sel_tri<2>.D 33.400
cntr_cnt<1>.Q demux_chip_sel_tri<0>.D 33.400
cntr_cnt<1>.Q demux_chip_sel_tri<1>.D 33.400
cntr_cnt<1>.Q demux_chip_sel_tri<2>.D 33.400
cntr_cnt<2>.Q demux_chip_sel_tri<0>.D 33.400
cntr_cnt<2>.Q demux_chip_sel_tri<1>.D 33.400
cntr_cnt<2>.Q demux_chip_sel_tri<2>.D 33.400
cntr_cnt<3>.Q demux_chip_sel_tri<0>.D 33.400
cntr_cnt<3>.Q demux_chip_sel_tri<1>.D 33.400
cntr_cnt<3>.Q demux_chip_sel_tri<2>.D 33.400
cntr_cnt<4>.Q demux_chip_sel_tri<0>.D 33.400
cntr_cnt<4>.Q demux_chip_sel_tri<1>.D 33.400
cntr_cnt<4>.Q demux_chip_sel_tri<2>.D 33.400
cntr_cnt<5>.Q demux_chip_sel_tri<0>.D 33.400
cntr_cnt<5>.Q demux_chip_sel_tri<1>.D 33.400
cntr_cnt<5>.Q demux_chip_sel_tri<2>.D 33.400
cntr_cnt<6>.Q demux_chip_sel_tri<0>.D 33.400
cntr_cnt<6>.Q demux_chip_sel_tri<1>.D 33.400
cntr_cnt<6>.Q demux_chip_sel_tri<2>.D 33.400
cntr_cnt<7>.Q demux_chip_sel_tri<0>.D 33.400
cntr_cnt<7>.Q demux_chip_sel_tri<1>.D 33.400
cntr_cnt<7>.Q demux_chip_sel_tri<2>.D 33.400
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/CHIP_IDLE.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/CHIP_READ2.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q SAN_BUFR.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q cntr_tri.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q col_clk_BUFR.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q sel_clk_BUFR.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q status_reg_data<1>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q col_clk_BUFR.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q status_reg_data<0>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q status_reg_data<2>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q status_reg_data<0>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q status_reg_data<2>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q status_reg_data<3>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q post_sleep.D 32.200
FSM/SHELL1_DSP_SM_2/CLR_0.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/CLR_0.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/CLR_0.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/CLR_1.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/CLR_1.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/CLR_1.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/CLR_2.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/CLR_2.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/CLR_2.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q cntr_sel.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q cntr_set_value<0>.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q cntr_set_value<2>.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_READ.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_READ.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_READ.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_READ.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_READ.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_READ.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_READ.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_READ.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_READ.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_READ.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_READ.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q cntr_sel.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q cntr_set_value<0>.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q cntr_set_value<2>.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/XMIT_END.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/XMIT_END.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/XMIT_END.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 32.200
FSM/SHELL1_DSP_SM_2/XMIT_END.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 32.200
FSM/SHELL1_DSP_SM_2/XMIT_END.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 32.200
FSM/SHELL1_DSP_SM_2/XMIT_END.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/XMIT_END.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 32.200
FSM/SHELL1_DSP_SM_2/XMIT_END.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/XMIT_END.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/XMIT_END.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/XMIT_END.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 32.200
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 32.200
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 32.200
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 32.200
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 32.200
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 32.200
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q demux_chip_sel_tri<0>.D 32.200
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q demux_chip_sel_tri<1>.D 32.200
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q demux_chip_sel_tri<2>.D 32.200
FSM/SHELL1_DSP_SM_2/ramp_cnt0.Q cntr_sel.D 32.200
FSM/SHELL1_DSP_SM_2/ramp_cnt0.Q cntr_set_value<0>.D 32.200
FSM/SHELL1_DSP_SM_2/ramp_cnt0.Q cntr_set_value<2>.D 32.200
FSM/SHELL1_DSP_SM_2/ramp_cnt1.Q cntr_sel.D 32.200
FSM/SHELL1_DSP_SM_2/ramp_cnt1.Q cntr_set_value<0>.D 32.200
FSM/SHELL1_DSP_SM_2/ramp_cnt1.Q cntr_set_value<2>.D 32.200
FSM/SHELL1_DSP_SM_2/ramp_cnt2.Q cntr_sel.D 32.200
FSM/SHELL1_DSP_SM_2/ramp_cnt2.Q cntr_set_value<0>.D 32.200
FSM/SHELL1_DSP_SM_2/ramp_cnt2.Q cntr_set_value<2>.D 32.200
FSM/SHELL1_DSP_SM_2/ramp_cnt3.Q cntr_sel.D 32.200
FSM/SHELL1_DSP_SM_2/ramp_cnt3.Q cntr_set_value<0>.D 32.200
FSM/SHELL1_DSP_SM_2/ramp_cnt3.Q cntr_set_value<2>.D 32.200
FSM/SHELL1_DSP_SM_2/ramp_cnt4.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 32.200
FSM/SHELL1_DSP_SM_2/ramp_cnt4.Q cntr_sel.D 32.200
FSM/SHELL1_DSP_SM_2/ramp_cnt4.Q cntr_set_value<0>.D 32.200
FSM/SHELL1_DSP_SM_2/ramp_cnt4.Q cntr_set_value<2>.D 32.200
FSM/SHELL1_DSP_SM_2/ramp_cnt5.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 32.200
FSM/SHELL1_DSP_SM_2/ramp_cnt5.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 32.200
FSM/SHELL1_DSP_SM_2/ramp_cnt5.Q cntr_sel.D 32.200
FSM/SHELL1_DSP_SM_2/ramp_cnt5.Q cntr_set_value<0>.D 32.200
FSM/SHELL1_DSP_SM_2/ramp_cnt5.Q cntr_set_value<2>.D 32.200
FSM/SHELL1_DSP_SM_2/ramp_cnt6.Q cntr_sel.D 32.200
FSM/SHELL1_DSP_SM_2/ramp_cnt6.Q cntr_set_value<0>.D 32.200
FSM/SHELL1_DSP_SM_2/ramp_cnt6.Q cntr_set_value<2>.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt0.Q FSM/SHELL1_DSP_SM_2/CHIP_IDLE.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt0.Q FSM/SHELL1_DSP_SM_2/CHIP_READ2.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt0.Q SAN_BUFR.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt0.Q cntr_tri.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt0.Q col_clk_BUFR.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt0.Q sel_clk_BUFR.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt0.Q status_reg_data<1>.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt1.Q FSM/SHELL1_DSP_SM_2/CHIP_IDLE.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt1.Q FSM/SHELL1_DSP_SM_2/CHIP_READ2.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt1.Q SAN_BUFR.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt1.Q cntr_tri.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt1.Q col_clk_BUFR.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt1.Q sel_clk_BUFR.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt1.Q status_reg_data<1>.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt2.Q FSM/SHELL1_DSP_SM_2/CHIP_IDLE.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt2.Q FSM/SHELL1_DSP_SM_2/CHIP_READ2.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt2.Q SAN_BUFR.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt2.Q cntr_tri.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt2.Q col_clk_BUFR.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt2.Q sel_clk_BUFR.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt2.Q status_reg_data<1>.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt3.Q FSM/SHELL1_DSP_SM_2/CHIP_IDLE.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt3.Q FSM/SHELL1_DSP_SM_2/CHIP_READ2.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt3.Q SAN_BUFR.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt3.Q cntr_tri.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt3.Q col_clk_BUFR.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt3.Q sel_clk_BUFR.D 32.200
FSM/SHELL1_DSP_SM_2/row_cnt3.Q status_reg_data<1>.D 32.200
FSM/SHELL1_DSP_SM_2/sel_cnt0.Q col_clk_BUFR.D 32.200
FSM/SHELL1_DSP_SM_2/sel_cnt0.Q status_reg_data<0>.D 32.200
FSM/SHELL1_DSP_SM_2/sel_cnt0.Q status_reg_data<2>.D 32.200
FSM/SHELL1_DSP_SM_2/sel_cnt1.Q col_clk_BUFR.D 32.200
FSM/SHELL1_DSP_SM_2/sel_cnt1.Q status_reg_data<0>.D 32.200
FSM/SHELL1_DSP_SM_2/sel_cnt1.Q status_reg_data<2>.D 32.200
FSM/SHELL1_DSP_SM_2/sel_cnt2.Q col_clk_BUFR.D 32.200
FSM/SHELL1_DSP_SM_2/sel_cnt2.Q status_reg_data<0>.D 32.200
FSM/SHELL1_DSP_SM_2/sel_cnt2.Q status_reg_data<2>.D 32.200
FSM/SHELL1_DSP_SM_2/sel_cnt3.Q col_clk_BUFR.D 32.200
FSM/SHELL1_DSP_SM_2/sel_cnt3.Q status_reg_data<0>.D 32.200
FSM/SHELL1_DSP_SM_2/sel_cnt3.Q status_reg_data<2>.D 32.200
cntr_cnt<0>.Q SH_samp_0.D 32.200
cntr_cnt<0>.Q demux_chip_sel_tri<3>.D 32.200
cntr_cnt<0>.Q post_sleep.D 32.200
cntr_cnt<0>.Q status_reg_data<1>.D 32.200
cntr_cnt<0>.Q status_reg_load.D 32.200
cntr_cnt<1>.Q SH_samp_0.D 32.200
cntr_cnt<1>.Q demux_chip_sel_tri<3>.D 32.200
cntr_cnt<1>.Q post_sleep.D 32.200
cntr_cnt<1>.Q status_reg_data<1>.D 32.200
cntr_cnt<1>.Q status_reg_load.D 32.200
cntr_cnt<2>.Q SH_samp_0.D 32.200
cntr_cnt<2>.Q demux_chip_sel_tri<3>.D 32.200
cntr_cnt<2>.Q post_sleep.D 32.200
cntr_cnt<2>.Q status_reg_data<1>.D 32.200
cntr_cnt<2>.Q status_reg_load.D 32.200
cntr_cnt<3>.Q SH_samp_0.D 32.200
cntr_cnt<3>.Q demux_chip_sel_tri<3>.D 32.200
cntr_cnt<3>.Q post_sleep.D 32.200
cntr_cnt<3>.Q status_reg_data<1>.D 32.200
cntr_cnt<3>.Q status_reg_load.D 32.200
cntr_cnt<4>.Q SH_samp_0.D 32.200
cntr_cnt<4>.Q demux_chip_sel_tri<3>.D 32.200
cntr_cnt<4>.Q post_sleep.D 32.200
cntr_cnt<4>.Q status_reg_data<1>.D 32.200
cntr_cnt<4>.Q status_reg_load.D 32.200
cntr_cnt<5>.Q SH_samp_0.D 32.200
cntr_cnt<5>.Q demux_chip_sel_tri<3>.D 32.200
cntr_cnt<5>.Q post_sleep.D 32.200
cntr_cnt<5>.Q status_reg_data<1>.D 32.200
cntr_cnt<5>.Q status_reg_load.D 32.200
cntr_cnt<6>.Q SH_samp_0.D 32.200
cntr_cnt<6>.Q demux_chip_sel_tri<3>.D 32.200
cntr_cnt<6>.Q post_sleep.D 32.200
cntr_cnt<6>.Q status_reg_data<1>.D 32.200
cntr_cnt<6>.Q status_reg_load.D 32.200
cntr_cnt<7>.Q SH_samp_0.D 32.200
cntr_cnt<7>.Q demux_chip_sel_tri<3>.D 32.200
cntr_cnt<7>.Q post_sleep.D 32.200
cntr_cnt<7>.Q status_reg_data<1>.D 32.200
cntr_cnt<7>.Q status_reg_load.D 32.200
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 31.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 31.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q row_clk_BUFR.D 31.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q transmit.D 31.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 31.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 31.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 31.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 31.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q cntr_8.D 31.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q cntr_9.D 31.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q cntr_set_value<1>.D 31.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q cntr_set_value<3>.D 31.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q cntr_set_value<5>.D 31.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q sel_pulse_BUFR.D 31.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 31.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q status_reg_data<2>.D 31.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q status_reg_load.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt0.Q cntr_8.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt0.Q cntr_9.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt0.Q cntr_set_value<1>.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt0.Q cntr_set_value<3>.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt0.Q cntr_set_value<5>.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt0.Q sel_pulse_BUFR.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt2.Q cntr_8.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt2.Q cntr_9.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt2.Q cntr_set_value<1>.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt2.Q cntr_set_value<3>.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt2.Q cntr_set_value<5>.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt2.Q sel_pulse_BUFR.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt3.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt3.Q cntr_8.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt3.Q cntr_9.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt3.Q cntr_set_value<1>.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt3.Q cntr_set_value<3>.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt3.Q cntr_set_value<5>.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt3.Q sel_pulse_BUFR.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt4.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt4.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt4.Q cntr_8.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt4.Q cntr_9.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt4.Q cntr_set_value<1>.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt4.Q cntr_set_value<3>.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt4.Q cntr_set_value<5>.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt4.Q sel_pulse_BUFR.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt5.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt5.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt5.Q cntr_8.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt5.Q cntr_9.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt5.Q cntr_set_value<1>.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt5.Q cntr_set_value<3>.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt5.Q cntr_set_value<5>.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt5.Q sel_pulse_BUFR.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt6.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt6.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt6.Q cntr_8.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt6.Q cntr_9.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt6.Q cntr_set_value<1>.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt6.Q cntr_set_value<3>.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt6.Q cntr_set_value<5>.D 31.000
FSM/SHELL1_DSP_SM_2/ramp_cnt6.Q sel_pulse_BUFR.D 31.000
FSM/SHELL1_DSP_SM_2/ramps0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 31.000
FSM/SHELL1_DSP_SM_2/ramps0.Q status_reg_data<2>.D 31.000
FSM/SHELL1_DSP_SM_2/ramps0.Q status_reg_load.D 31.000
FSM/SHELL1_DSP_SM_2/ramps1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 31.000
FSM/SHELL1_DSP_SM_2/ramps1.Q status_reg_data<2>.D 31.000
FSM/SHELL1_DSP_SM_2/ramps1.Q status_reg_load.D 31.000
FSM/SHELL1_DSP_SM_2/sel_cnt0.Q row_clk_BUFR.D 31.000
FSM/SHELL1_DSP_SM_2/sel_cnt1.Q row_clk_BUFR.D 31.000
FSM/SHELL1_DSP_SM_2/sel_cnt2.Q row_clk_BUFR.D 31.000
FSM/SHELL1_DSP_SM_2/sel_cnt3.Q row_clk_BUFR.D 31.000
cntr_cnt<0>.Q FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.D 31.000
cntr_cnt<1>.Q FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.D 31.000
cntr_cnt<2>.Q FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.D 31.000
cntr_cnt<3>.Q FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.D 31.000
cntr_cnt<4>.Q FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.D 31.000
cntr_cnt<5>.Q FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.D 31.000
cntr_cnt<6>.Q FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.D 31.000
cntr_cnt<7>.Q FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.D 31.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/RAMP_S1.D 29.800
FSM/SHELL1_DSP_SM_2/ramp_cnt0.Q FSM/SHELL1_DSP_SM_2/RAMP_S1.D 29.800
FSM/SHELL1_DSP_SM_2/ramp_cnt2.Q FSM/SHELL1_DSP_SM_2/RAMP_S1.D 29.800
FSM/SHELL1_DSP_SM_2/ramp_cnt3.Q FSM/SHELL1_DSP_SM_2/RAMP_S1.D 29.800
FSM/SHELL1_DSP_SM_2/ramp_cnt4.Q FSM/SHELL1_DSP_SM_2/RAMP_S1.D 29.800
FSM/SHELL1_DSP_SM_2/ramp_cnt5.Q FSM/SHELL1_DSP_SM_2/RAMP_S1.D 29.800
FSM/SHELL1_DSP_SM_2/ramp_cnt6.Q FSM/SHELL1_DSP_SM_2/RAMP_S1.D 29.800
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q status_reg_data<0>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q status_reg_data<2>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q PRE.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q SAN_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q cntr_tri.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q col_clk_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q sel_clk_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q status_reg_data<1>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q status_reg_load.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q chip_sel<1>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q demux_chip_sel_tri<3>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q status_reg_data<0>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q status_reg_data<2>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/IDLE.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q chip_sel<1>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q demux_dsp_sel_load<0>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q demux_dsp_sel_load<1>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q demux_dsp_sel_load<2>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q demux_dsp_sel_load<3>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q demux_dsp_sel_tri<0>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q demux_dsp_sel_tri<1>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q demux_dsp_sel_tri<2>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q demux_dsp_sel_tri<3>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q sel_clk_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q status_reg_data<0>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q status_reg_data<2>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q status_reg_data<0>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q status_reg_data<2>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q demux_chip_sel_tri<3>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q status_reg_data<0>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q status_reg_data<2>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q status_reg_data<0>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q status_reg_data<2>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q status_reg_data<0>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q status_reg_data<2>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q PRE.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q status_reg_load.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q status_reg_data<0>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q status_reg_data<2>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q PRE.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q status_reg_load.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q status_reg_data<0>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q status_reg_data<2>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q demux_chip_sel_tri<3>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q status_reg_data<0>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q status_reg_data<2>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0.Q status_reg_data<0>.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0.Q status_reg_data<2>.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q chip_sel<1>.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q col_clk_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q sel_clk_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q status_reg_data<0>.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q status_reg_data<2>.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1.Q status_reg_data<0>.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1.Q status_reg_data<2>.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q chip_sel<1>.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q sel_clk_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q status_reg_data<0>.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q status_reg_data<2>.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2.Q SAN_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2.Q cntr_tri.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2.Q col_clk_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2.Q sel_clk_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2.Q status_reg_data<1>.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q chip_sel<1>.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q sel_clk_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q status_reg_data<0>.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q status_reg_data<2>.D 23.200
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/DONE_READ.Q FSM/SHELL1_DSP_SM_2/IDLE.D 23.200
FSM/SHELL1_DSP_SM_2/DONE_READ.Q demux_dsp_sel_load<0>.D 23.200
FSM/SHELL1_DSP_SM_2/DONE_READ.Q demux_dsp_sel_load<1>.D 23.200
FSM/SHELL1_DSP_SM_2/DONE_READ.Q demux_dsp_sel_load<2>.D 23.200
FSM/SHELL1_DSP_SM_2/DONE_READ.Q demux_dsp_sel_load<3>.D 23.200
FSM/SHELL1_DSP_SM_2/DONE_READ.Q demux_dsp_sel_tri<0>.D 23.200
FSM/SHELL1_DSP_SM_2/DONE_READ.Q demux_dsp_sel_tri<1>.D 23.200
FSM/SHELL1_DSP_SM_2/DONE_READ.Q demux_dsp_sel_tri<2>.D 23.200
FSM/SHELL1_DSP_SM_2/DONE_READ.Q demux_dsp_sel_tri<3>.D 23.200
FSM/SHELL1_DSP_SM_2/DSP_WRITE.Q FSM/SHELL1_DSP_SM_2/IDLE.D 23.200
FSM/SHELL1_DSP_SM_2/DSP_WRITE.Q demux_dsp_sel_load<0>.D 23.200
FSM/SHELL1_DSP_SM_2/DSP_WRITE.Q demux_dsp_sel_load<1>.D 23.200
FSM/SHELL1_DSP_SM_2/DSP_WRITE.Q demux_dsp_sel_load<2>.D 23.200
FSM/SHELL1_DSP_SM_2/DSP_WRITE.Q demux_dsp_sel_load<3>.D 23.200
FSM/SHELL1_DSP_SM_2/DSP_WRITE.Q demux_dsp_sel_tri<0>.D 23.200
FSM/SHELL1_DSP_SM_2/DSP_WRITE.Q demux_dsp_sel_tri<1>.D 23.200
FSM/SHELL1_DSP_SM_2/DSP_WRITE.Q demux_dsp_sel_tri<2>.D 23.200
FSM/SHELL1_DSP_SM_2/DSP_WRITE.Q demux_dsp_sel_tri<3>.D 23.200
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 23.200
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q cntr_set_value<6>.D 23.200
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q cntr_tri.D 23.200
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q demux_chip_sel_tri<3>.D 23.200
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q status_reg_data<0>.D 23.200
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q status_reg_data<2>.D 23.200
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/PRE_READ.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/PRE_READ.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/PRE_READ.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/PRE_READ.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/PRE_READ.Q demux_chip_sel_tri<3>.D 23.200
FSM/SHELL1_DSP_SM_2/PRE_READ.Q status_reg_data<0>.D 23.200
FSM/SHELL1_DSP_SM_2/PRE_READ.Q status_reg_data<2>.D 23.200
FSM/SHELL1_DSP_SM_2/PRE_READ.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q cntr_set_value<6>.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q cntr_tri.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q demux_chip_sel_tri<3>.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q status_reg_data<0>.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q status_reg_data<2>.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q status_reg_data<0>.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q status_reg_data<2>.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q demux_chip_sel_tri<0>.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q demux_chip_sel_tri<1>.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q demux_chip_sel_tri<2>.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q status_reg_data<0>.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q status_reg_data<2>.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q cntr_set_value<6>.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q cntr_tri.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q demux_chip_sel_tri<3>.D 23.200
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q status_reg_data<1>.D 23.200
FSM/SHELL1_DSP_SM_2/WRITE_STATUS.Q FSM/SHELL1_DSP_SM_2/IDLE.D 23.200
FSM/SHELL1_DSP_SM_2/WRITE_STATUS.Q demux_dsp_sel_load<0>.D 23.200
FSM/SHELL1_DSP_SM_2/WRITE_STATUS.Q demux_dsp_sel_load<1>.D 23.200
FSM/SHELL1_DSP_SM_2/WRITE_STATUS.Q demux_dsp_sel_load<2>.D 23.200
FSM/SHELL1_DSP_SM_2/WRITE_STATUS.Q demux_dsp_sel_load<3>.D 23.200
FSM/SHELL1_DSP_SM_2/WRITE_STATUS.Q demux_dsp_sel_tri<0>.D 23.200
FSM/SHELL1_DSP_SM_2/WRITE_STATUS.Q demux_dsp_sel_tri<1>.D 23.200
FSM/SHELL1_DSP_SM_2/WRITE_STATUS.Q demux_dsp_sel_tri<2>.D 23.200
FSM/SHELL1_DSP_SM_2/WRITE_STATUS.Q demux_dsp_sel_tri<3>.D 23.200
FSM/SHELL1_DSP_SM_2/WRITE_XMIT.Q FSM/SHELL1_DSP_SM_2/IDLE.D 23.200
FSM/SHELL1_DSP_SM_2/WRITE_XMIT.Q demux_dsp_sel_load<0>.D 23.200
FSM/SHELL1_DSP_SM_2/WRITE_XMIT.Q demux_dsp_sel_load<1>.D 23.200
FSM/SHELL1_DSP_SM_2/WRITE_XMIT.Q demux_dsp_sel_load<2>.D 23.200
FSM/SHELL1_DSP_SM_2/WRITE_XMIT.Q demux_dsp_sel_load<3>.D 23.200
FSM/SHELL1_DSP_SM_2/WRITE_XMIT.Q demux_dsp_sel_tri<0>.D 23.200
FSM/SHELL1_DSP_SM_2/WRITE_XMIT.Q demux_dsp_sel_tri<1>.D 23.200
FSM/SHELL1_DSP_SM_2/WRITE_XMIT.Q demux_dsp_sel_tri<2>.D 23.200
FSM/SHELL1_DSP_SM_2/WRITE_XMIT.Q demux_dsp_sel_tri<3>.D 23.200
FSM/SHELL1_DSP_SM_2/XMIT_END.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/XMIT_END.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/XMIT_END.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/XMIT_END.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q demux_chip_sel_tri<3>.D 23.200
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q status_reg_data<0>.D 23.200
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q status_reg_data<2>.D 23.200
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 23.200
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 23.200
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q status_reg_data<0>.D 23.200
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q status_reg_data<2>.D 23.200
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt0.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt0.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt0.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt0.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt0.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt0.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt0.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt0.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt0.Q PRE.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt0.Q SAN_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt0.Q chip_sel<1>.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt0.Q cntr_tri.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt0.Q col_clk_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt0.Q sel_clk_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt0.Q status_reg_data<1>.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt0.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt0.Q status_reg_load.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt1.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt1.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt1.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt1.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt1.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt1.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt1.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt1.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt1.Q PRE.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt1.Q SAN_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt1.Q chip_sel<1>.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt1.Q cntr_tri.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt1.Q col_clk_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt1.Q sel_clk_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt1.Q status_reg_data<1>.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt1.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt1.Q status_reg_load.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt2.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt2.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt2.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt2.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt2.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt2.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt2.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt2.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt2.Q PRE.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt2.Q SAN_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt2.Q chip_sel<1>.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt2.Q cntr_tri.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt2.Q col_clk_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt2.Q sel_clk_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt2.Q status_reg_data<1>.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt2.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt2.Q status_reg_load.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt3.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt3.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt3.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt3.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt3.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt3.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt3.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt3.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt3.Q PRE.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt3.Q SAN_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt3.Q chip_sel<1>.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt3.Q cntr_tri.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt3.Q col_clk_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt3.Q sel_clk_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt3.Q status_reg_data<1>.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt3.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt3.Q status_reg_load.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt4.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt4.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt4.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt4.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt4.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt4.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt4.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt4.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt4.Q PRE.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt4.Q SAN_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt4.Q chip_sel<1>.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt4.Q cntr_tri.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt4.Q col_clk_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt4.Q sel_clk_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt4.Q status_reg_data<1>.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt4.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt4.Q status_reg_load.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt5.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt5.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt5.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt5.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt5.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt5.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt5.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt5.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt5.Q PRE.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt5.Q SAN_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt5.Q chip_sel<1>.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt5.Q cntr_tri.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt5.Q col_clk_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt5.Q sel_clk_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt5.Q status_reg_data<1>.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt5.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/col_cnt5.Q status_reg_load.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt0.Q cntr_set_value<6>.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt0.Q cntr_tri.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt1.Q cntr_set_value<6>.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt1.Q cntr_tri.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt2.Q cntr_set_value<6>.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt2.Q cntr_tri.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt3.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt3.Q cntr_set_value<6>.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt3.Q cntr_tri.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt4.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt4.Q cntr_set_value<6>.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt4.Q cntr_tri.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt5.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt5.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt5.Q cntr_set_value<6>.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt5.Q cntr_tri.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt6.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt6.Q FSM/SHELL1_DSP_SM_2/ramp_cnt4.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt6.Q FSM/SHELL1_DSP_SM_2/ramp_cnt5.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt6.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt6.Q cntr_set_value<6>.D 23.200
FSM/SHELL1_DSP_SM_2/ramp_cnt6.Q cntr_tri.D 23.200
FSM/SHELL1_DSP_SM_2/ramps0.Q cntr_set_value<6>.D 23.200
FSM/SHELL1_DSP_SM_2/ramps0.Q cntr_tri.D 23.200
FSM/SHELL1_DSP_SM_2/ramps0.Q status_reg_data<1>.D 23.200
FSM/SHELL1_DSP_SM_2/ramps1.Q cntr_set_value<6>.D 23.200
FSM/SHELL1_DSP_SM_2/ramps1.Q cntr_tri.D 23.200
FSM/SHELL1_DSP_SM_2/ramps1.Q status_reg_data<1>.D 23.200
FSM/SHELL1_DSP_SM_2/row_cnt0.Q chip_sel<1>.D 23.200
FSM/SHELL1_DSP_SM_2/row_cnt1.Q chip_sel<1>.D 23.200
FSM/SHELL1_DSP_SM_2/row_cnt2.Q chip_sel<1>.D 23.200
FSM/SHELL1_DSP_SM_2/row_cnt3.Q chip_sel<1>.D 23.200
FSM/SHELL1_DSP_SM_2/sel_cnt0.Q PRE.D 23.200
FSM/SHELL1_DSP_SM_2/sel_cnt0.Q chip_sel<1>.D 23.200
FSM/SHELL1_DSP_SM_2/sel_cnt0.Q sel_clk_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/sel_cnt0.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/sel_cnt0.Q status_reg_load.D 23.200
FSM/SHELL1_DSP_SM_2/sel_cnt1.Q PRE.D 23.200
FSM/SHELL1_DSP_SM_2/sel_cnt1.Q chip_sel<1>.D 23.200
FSM/SHELL1_DSP_SM_2/sel_cnt1.Q sel_clk_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/sel_cnt1.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/sel_cnt1.Q status_reg_load.D 23.200
FSM/SHELL1_DSP_SM_2/sel_cnt2.Q PRE.D 23.200
FSM/SHELL1_DSP_SM_2/sel_cnt2.Q chip_sel<1>.D 23.200
FSM/SHELL1_DSP_SM_2/sel_cnt2.Q sel_clk_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/sel_cnt2.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/sel_cnt2.Q status_reg_load.D 23.200
FSM/SHELL1_DSP_SM_2/sel_cnt3.Q PRE.D 23.200
FSM/SHELL1_DSP_SM_2/sel_cnt3.Q chip_sel<1>.D 23.200
FSM/SHELL1_DSP_SM_2/sel_cnt3.Q sel_clk_BUFR.D 23.200
FSM/SHELL1_DSP_SM_2/sel_cnt3.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/sel_cnt3.Q status_reg_load.D 23.200
FSM/SHELL1_DSP_SM_2/tochip_command0.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 23.200
FSM/SHELL1_DSP_SM_2/tochip_command0.Q status_reg_data<0>.D 23.200
FSM/SHELL1_DSP_SM_2/tochip_command0.Q status_reg_data<2>.D 23.200
FSM/SHELL1_DSP_SM_2/tochip_command1.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 23.200
FSM/SHELL1_DSP_SM_2/tochip_command1.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 23.200
FSM/SHELL1_DSP_SM_2/tochip_command1.Q status_reg_data<0>.D 23.200
FSM/SHELL1_DSP_SM_2/tochip_command1.Q status_reg_data<2>.D 23.200
FSM/SHELL1_DSP_SM_2/todsp_command0.Q FSM/SHELL1_DSP_SM_2/IDLE.D 23.200
FSM/SHELL1_DSP_SM_2/todsp_command0.Q demux_dsp_sel_load<0>.D 23.200
FSM/SHELL1_DSP_SM_2/todsp_command0.Q demux_dsp_sel_load<1>.D 23.200
FSM/SHELL1_DSP_SM_2/todsp_command0.Q demux_dsp_sel_load<2>.D 23.200
FSM/SHELL1_DSP_SM_2/todsp_command0.Q demux_dsp_sel_load<3>.D 23.200
FSM/SHELL1_DSP_SM_2/todsp_command0.Q demux_dsp_sel_tri<0>.D 23.200
FSM/SHELL1_DSP_SM_2/todsp_command0.Q demux_dsp_sel_tri<1>.D 23.200
FSM/SHELL1_DSP_SM_2/todsp_command0.Q demux_dsp_sel_tri<2>.D 23.200
FSM/SHELL1_DSP_SM_2/todsp_command0.Q demux_dsp_sel_tri<3>.D 23.200
FSM/SHELL1_DSP_SM_2/todsp_command1.Q FSM/SHELL1_DSP_SM_2/IDLE.D 23.200
FSM/SHELL1_DSP_SM_2/todsp_command1.Q demux_dsp_sel_load<0>.D 23.200
FSM/SHELL1_DSP_SM_2/todsp_command1.Q demux_dsp_sel_load<1>.D 23.200
FSM/SHELL1_DSP_SM_2/todsp_command1.Q demux_dsp_sel_load<2>.D 23.200
FSM/SHELL1_DSP_SM_2/todsp_command1.Q demux_dsp_sel_load<3>.D 23.200
FSM/SHELL1_DSP_SM_2/todsp_command1.Q demux_dsp_sel_tri<0>.D 23.200
FSM/SHELL1_DSP_SM_2/todsp_command1.Q demux_dsp_sel_tri<1>.D 23.200
FSM/SHELL1_DSP_SM_2/todsp_command1.Q demux_dsp_sel_tri<2>.D 23.200
FSM/SHELL1_DSP_SM_2/todsp_command1.Q demux_dsp_sel_tri<3>.D 23.200
cntr_cnt<0>.Q FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.D 23.200
cntr_cnt<0>.Q FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.D 23.200
cntr_cnt<1>.Q FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.D 23.200
cntr_cnt<1>.Q FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.D 23.200
cntr_cnt<2>.Q FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.D 23.200
cntr_cnt<2>.Q FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.D 23.200
cntr_cnt<3>.Q FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.D 23.200
cntr_cnt<3>.Q FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.D 23.200
cntr_cnt<4>.Q FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.D 23.200
cntr_cnt<4>.Q FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.D 23.200
cntr_cnt<5>.Q FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.D 23.200
cntr_cnt<5>.Q FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.D 23.200
cntr_cnt<6>.Q FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.D 23.200
cntr_cnt<6>.Q FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.D 23.200
cntr_cnt<7>.Q FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.D 23.200
cntr_cnt<7>.Q FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.D 23.200
status_reg_data<3>.Q status_reg_data<3>.D 23.200
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q row_clk_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q status_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/CHIP_READ2.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q row_clk_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q status_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/CLR_0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q row_clk_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q status_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q row_clk_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q status_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q row_clk_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q status_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q row_clk_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q status_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q row_clk_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q status_reg_data<2>.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q status_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q status_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q FSM/SHELL1_DSP_SM_2/CHIP_READ2.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q row_clk_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q status_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/CHIP_READ2.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q SAN_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q cntr_tri.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q sel_clk_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q sel_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q status_reg_data<1>.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q demux_chip_sel_tri<3>.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q row_clk_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q status_reg_data<1>.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q status_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q row_clk_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q status_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q row_clk_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q status_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q row_clk_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q status_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/CLR_0.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q row_clk_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q status_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q row_clk_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q status_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/CLR_0.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q row_clk_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q status_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q status_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/CLR_0.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q row_clk_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q status_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q FSM/SHELL1_DSP_SM_2/RAMP_S0.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q row_clk_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q status_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q row_clk_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q status_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q row_clk_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q status_reg_data<2>.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q status_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/RAMP_S0.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q row_clk_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q status_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q row_clk_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q status_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q row_clk_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q status_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/RAMP_S0.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q cntr_sel.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q cntr_set_value<0>.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q cntr_set_value<1>.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q cntr_set_value<2>.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q cntr_set_value<3>.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q row_clk_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q sample_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q sel_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q row_clk_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q row_clk_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q status_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/ramps1.D 22.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 22.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q SH_samp_0.D 22.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q dac_en.D 22.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q pre_sleep_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q row_clk_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q row_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q status_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q transmit.D 22.000
FSM/SHELL1_DSP_SM_2/col_cnt0.Q FSM/SHELL1_DSP_SM_2/CHIP_READ2.D 22.000
FSM/SHELL1_DSP_SM_2/col_cnt0.Q FSM/SHELL1_DSP_SM_2/CLR_0.D 22.000
FSM/SHELL1_DSP_SM_2/col_cnt1.Q FSM/SHELL1_DSP_SM_2/CHIP_READ2.D 22.000
FSM/SHELL1_DSP_SM_2/col_cnt1.Q FSM/SHELL1_DSP_SM_2/CLR_0.D 22.000
FSM/SHELL1_DSP_SM_2/col_cnt2.Q FSM/SHELL1_DSP_SM_2/CHIP_READ2.D 22.000
FSM/SHELL1_DSP_SM_2/col_cnt2.Q FSM/SHELL1_DSP_SM_2/CLR_0.D 22.000
FSM/SHELL1_DSP_SM_2/col_cnt3.Q FSM/SHELL1_DSP_SM_2/CHIP_READ2.D 22.000
FSM/SHELL1_DSP_SM_2/col_cnt3.Q FSM/SHELL1_DSP_SM_2/CLR_0.D 22.000
FSM/SHELL1_DSP_SM_2/col_cnt4.Q FSM/SHELL1_DSP_SM_2/CHIP_READ2.D 22.000
FSM/SHELL1_DSP_SM_2/col_cnt4.Q FSM/SHELL1_DSP_SM_2/CLR_0.D 22.000
FSM/SHELL1_DSP_SM_2/col_cnt5.Q FSM/SHELL1_DSP_SM_2/CHIP_READ2.D 22.000
FSM/SHELL1_DSP_SM_2/col_cnt5.Q FSM/SHELL1_DSP_SM_2/CLR_0.D 22.000
FSM/SHELL1_DSP_SM_2/ramp_cnt0.Q FSM/SHELL1_DSP_SM_2/RAMP_S0.D 22.000
FSM/SHELL1_DSP_SM_2/ramp_cnt0.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/ramp_cnt1.Q FSM/SHELL1_DSP_SM_2/RAMP_S0.D 22.000
FSM/SHELL1_DSP_SM_2/ramp_cnt1.Q cntr_8.D 22.000
FSM/SHELL1_DSP_SM_2/ramp_cnt1.Q cntr_9.D 22.000
FSM/SHELL1_DSP_SM_2/ramp_cnt1.Q cntr_set_value<1>.D 22.000
FSM/SHELL1_DSP_SM_2/ramp_cnt1.Q cntr_set_value<3>.D 22.000
FSM/SHELL1_DSP_SM_2/ramp_cnt1.Q cntr_set_value<5>.D 22.000
FSM/SHELL1_DSP_SM_2/ramp_cnt1.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/ramp_cnt1.Q sel_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/ramp_cnt2.Q FSM/SHELL1_DSP_SM_2/RAMP_S0.D 22.000
FSM/SHELL1_DSP_SM_2/ramp_cnt2.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/ramp_cnt3.Q FSM/SHELL1_DSP_SM_2/RAMP_S0.D 22.000
FSM/SHELL1_DSP_SM_2/ramp_cnt3.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/ramp_cnt4.Q FSM/SHELL1_DSP_SM_2/RAMP_S0.D 22.000
FSM/SHELL1_DSP_SM_2/ramp_cnt4.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/ramp_cnt5.Q FSM/SHELL1_DSP_SM_2/RAMP_S0.D 22.000
FSM/SHELL1_DSP_SM_2/ramp_cnt5.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/ramp_cnt6.Q FSM/SHELL1_DSP_SM_2/RAMP_S0.D 22.000
FSM/SHELL1_DSP_SM_2/ramp_cnt6.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/ramps0.Q FSM/SHELL1_DSP_SM_2/RAMP_S0.D 22.000
FSM/SHELL1_DSP_SM_2/ramps0.Q cntr_set_value<1>.D 22.000
FSM/SHELL1_DSP_SM_2/ramps0.Q cntr_set_value<3>.D 22.000
FSM/SHELL1_DSP_SM_2/ramps0.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/ramps0.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/ramps0.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/ramps0.Q sample_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/ramps0.Q sel_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/ramps1.Q FSM/SHELL1_DSP_SM_2/RAMP_S0.D 22.000
FSM/SHELL1_DSP_SM_2/ramps1.Q cntr_set_value<1>.D 22.000
FSM/SHELL1_DSP_SM_2/ramps1.Q cntr_set_value<3>.D 22.000
FSM/SHELL1_DSP_SM_2/ramps1.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/ramps1.Q comp_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/ramps1.Q post_sleep.D 22.000
FSM/SHELL1_DSP_SM_2/ramps1.Q sample_reg_load.D 22.000
FSM/SHELL1_DSP_SM_2/ramps1.Q sel_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/row_cnt0.Q FSM/SHELL1_DSP_SM_2/CLR_0.D 22.000
FSM/SHELL1_DSP_SM_2/row_cnt1.Q FSM/SHELL1_DSP_SM_2/CLR_0.D 22.000
FSM/SHELL1_DSP_SM_2/row_cnt2.Q FSM/SHELL1_DSP_SM_2/CLR_0.D 22.000
FSM/SHELL1_DSP_SM_2/row_cnt3.Q FSM/SHELL1_DSP_SM_2/CLR_0.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt0.Q FSM/SHELL1_DSP_SM_2/CHIP_READ2.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt0.Q FSM/SHELL1_DSP_SM_2/CLR_0.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt0.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt0.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt0.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt0.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt0.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt0.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt0.Q SAN_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt0.Q cntr_tri.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt0.Q sel_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt0.Q status_reg_data<1>.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt1.Q FSM/SHELL1_DSP_SM_2/CHIP_READ2.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt1.Q FSM/SHELL1_DSP_SM_2/CLR_0.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt1.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt1.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt1.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt1.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt1.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt1.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt1.Q SAN_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt1.Q cntr_tri.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt1.Q sel_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt1.Q status_reg_data<1>.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt2.Q FSM/SHELL1_DSP_SM_2/CHIP_READ2.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt2.Q FSM/SHELL1_DSP_SM_2/CLR_0.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt2.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt2.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt2.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt2.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt2.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt2.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt2.Q SAN_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt2.Q cntr_tri.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt2.Q sel_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt2.Q status_reg_data<1>.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt3.Q FSM/SHELL1_DSP_SM_2/CHIP_READ2.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt3.Q FSM/SHELL1_DSP_SM_2/CLR_0.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt3.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt3.Q FSM/SHELL1_DSP_SM_2/col_cnt1.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt3.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt3.Q FSM/SHELL1_DSP_SM_2/col_cnt3.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt3.Q FSM/SHELL1_DSP_SM_2/col_cnt4.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt3.Q FSM/SHELL1_DSP_SM_2/col_cnt5.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt3.Q SAN_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt3.Q cntr_tri.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt3.Q sel_pulse_BUFR.D 22.000
FSM/SHELL1_DSP_SM_2/sel_cnt3.Q status_reg_data<1>.D 22.000
cntr_set_value<7>.Q cntr_set_value<7>.D 22.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.D 20.800
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.D 20.800
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/PRE_READ.D 20.800
FSM/SHELL1_DSP_SM_2/ramp_cnt1.Q FSM/SHELL1_DSP_SM_2/RAMP_S1.D 20.800
FSM/SHELL1_DSP_SM_2/ramps0.Q FSM/SHELL1_DSP_SM_2/PRE_READ.D 20.800
FSM/SHELL1_DSP_SM_2/ramps1.Q FSM/SHELL1_DSP_SM_2/PRE_READ.D 20.800
FSM/SHELL1_DSP_SM_2/sel_cnt0.Q FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.D 20.800
FSM/SHELL1_DSP_SM_2/sel_cnt1.Q FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.D 20.800
FSM/SHELL1_DSP_SM_2/sel_cnt2.Q FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.D 20.800
FSM/SHELL1_DSP_SM_2/sel_cnt3.Q FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.D 20.800
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q PRE.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q SAN_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q chip_sel<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q cntr_tri.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q col_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q demux_chip_sel_tri<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q sel_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q status_reg_data<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q chip_sel<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q demux_chip_sel_tri<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q row_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q sel_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q demux_chip_sel_tri<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.Q sel_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/CHIP_IDLE.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q PRE.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q SAN_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q chip_sel<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q cntr_tri.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q col_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q sel_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q sel_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q status_reg_data<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q PRE.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q SAN_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q cntr_tri.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q col_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q demux_chip_sel_tri<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q sel_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_INIT.Q status_reg_data<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q FSM/SHELL1_DSP_SM_2/CHIP_IDLE.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q PRE.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q SAN_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q cntr_tri.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q col_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q demux_chip_sel_tri<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q sel_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q sel_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.Q status_reg_data<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q SAN_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q chip_sel<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q cntr_tri.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q col_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q sel_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q status_reg_data<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q PRE.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q SAN_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q chip_sel<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q cntr_tri.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q col_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q demux_chip_sel_tri<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q sel_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q sel_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q status_reg_data<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q PRE.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q SAN_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q chip_sel<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q cntr_tri.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q col_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q demux_chip_sel_tri<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q sel_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q sel_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q status_reg_data<0>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q status_reg_data<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q PRE.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q SAN_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q chip_sel<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q cntr_tri.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q col_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q demux_chip_sel_tri<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q row_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q row_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q sel_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q sel_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q status_reg_data<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q chip_sel<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q demux_chip_sel_tri<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_1.Q sel_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q FSM/SHELL1_DSP_SM_2/chip_read_5_1.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q PRE.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q SAN_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q cntr_tri.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q col_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q demux_chip_sel_tri<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q sel_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q sel_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_5.Q status_reg_data<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q chip_sel<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q demux_chip_sel_tri<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_READ_6.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q PRE.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q SAN_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q chip_sel<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q cntr_tri.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q col_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q sel_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.Q sel_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q PRE.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q SAN_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q chip_sel<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q cntr_tri.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q col_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q dac_en.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q demux_chip_sel_tri<0>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q demux_chip_sel_tri<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q demux_chip_sel_tri<2>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q demux_chip_sel_tri<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q pre_sleep_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q sel_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q sel_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q status_reg_data<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q PRE.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q SAN_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q chip_sel<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q cntr_tri.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q col_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q sel_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q sel_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q status_reg_data<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q PRE.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q SAN_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q chip_sel<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q cntr_tri.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q col_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q demux_chip_sel_tri<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q sel_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0.Q status_reg_data<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q PRE.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q SAN_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q cntr_tri.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q demux_chip_sel_tri<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q sel_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q status_reg_data<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q PRE.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q SAN_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q chip_sel<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q cntr_tri.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q demux_chip_sel_tri<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q sel_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q sel_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1.Q status_reg_data<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q PRE.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q SAN_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q cntr_tri.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q col_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q demux_chip_sel_tri<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q sel_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q status_reg_data<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q PRE.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q chip_sel<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q demux_chip_sel_tri<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2.Q sel_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/CHIP_IDLE.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q PRE.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q SAN_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q cntr_tri.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q col_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q demux_chip_sel_tri<3>.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q sel_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/CLR_2_1.Q status_reg_data<1>.D 13.000
FSM/SHELL1_DSP_SM_2/DONE_READ.Q FSM/SHELL1_DSP_SM_2/DONE_READ.D 13.000
FSM/SHELL1_DSP_SM_2/DONE_READ.Q FSM/SHELL1_DSP_SM_2/tochip_command1.D 13.000
FSM/SHELL1_DSP_SM_2/DSP_READ.Q FSM/SHELL1_DSP_SM_2/DONE_READ.D 13.000
FSM/SHELL1_DSP_SM_2/DSP_READ.Q FSM/SHELL1_DSP_SM_2/tochip_command1.D 13.000
FSM/SHELL1_DSP_SM_2/DSP_READ.Q demux_dsp_sel_load<0>.D 13.000
FSM/SHELL1_DSP_SM_2/DSP_READ.Q demux_dsp_sel_load<1>.D 13.000
FSM/SHELL1_DSP_SM_2/DSP_READ.Q demux_dsp_sel_load<2>.D 13.000
FSM/SHELL1_DSP_SM_2/DSP_READ.Q demux_dsp_sel_load<3>.D 13.000
FSM/SHELL1_DSP_SM_2/DSP_READ.Q demux_dsp_sel_tri<0>.D 13.000
FSM/SHELL1_DSP_SM_2/DSP_READ.Q demux_dsp_sel_tri<1>.D 13.000
FSM/SHELL1_DSP_SM_2/DSP_READ.Q demux_dsp_sel_tri<2>.D 13.000
FSM/SHELL1_DSP_SM_2/DSP_READ.Q demux_dsp_sel_tri<3>.D 13.000
FSM/SHELL1_DSP_SM_2/IDLE.Q FSM/SHELL1_DSP_SM_2/DSP_WRITE.D 13.000
FSM/SHELL1_DSP_SM_2/IDLE.Q FSM/SHELL1_DSP_SM_2/IDLE.D 13.000
FSM/SHELL1_DSP_SM_2/IDLE.Q FSM/SHELL1_DSP_SM_2/tochip_command0.D 13.000
FSM/SHELL1_DSP_SM_2/IDLE.Q FSM/SHELL1_DSP_SM_2/tochip_command1.D 13.000
FSM/SHELL1_DSP_SM_2/IDLE.Q demux_dsp_sel_load<0>.D 13.000
FSM/SHELL1_DSP_SM_2/IDLE.Q demux_dsp_sel_load<1>.D 13.000
FSM/SHELL1_DSP_SM_2/IDLE.Q demux_dsp_sel_load<2>.D 13.000
FSM/SHELL1_DSP_SM_2/IDLE.Q demux_dsp_sel_load<3>.D 13.000
FSM/SHELL1_DSP_SM_2/IDLE.Q demux_dsp_sel_tri<0>.D 13.000
FSM/SHELL1_DSP_SM_2/IDLE.Q demux_dsp_sel_tri<1>.D 13.000
FSM/SHELL1_DSP_SM_2/IDLE.Q demux_dsp_sel_tri<2>.D 13.000
FSM/SHELL1_DSP_SM_2/IDLE.Q demux_dsp_sel_tri<3>.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q FSM/SHELL1_DSP_SM_2/ramp_cnt6.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q PRE.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q SAN_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q chip_sel<1>.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q col_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q sel_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_RAMP.Q status_reg_data<1>.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q PRE.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q SAN_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q chip_sel<1>.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q cntr_tri.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q col_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q sel_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q sel_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ.Q status_reg_data<1>.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q PRE.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q SAN_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q chip_sel<1>.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q col_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q demux_chip_sel_tri<3>.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q sel_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q sel_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q status_reg_data<1>.D 13.000
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q status_reg_data<3>.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q PRE.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q SAN_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q chip_sel<1>.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q col_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q sel_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S0.Q status_reg_data<1>.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q PRE.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q SAN_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q chip_sel<1>.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q cntr_tri.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q col_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q demux_chip_sel_tri<3>.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q sel_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q sel_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q status_reg_data<1>.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q FSM/SHELL1_DSP_SM_2/ramps1.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q PRE.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q SAN_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q SH_samp_0.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q chip_sel<1>.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q cntr_8.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q cntr_9.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q cntr_tri.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q col_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q comp_sleep.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q dac_en.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q demux_chip_sel_tri<3>.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q pre_sleep_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q sel_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q status_reg_data<1>.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q PRE.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q SAN_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q chip_sel<1>.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q col_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/RAMP_S3.Q sel_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q PRE.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q SAN_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q chip_sel<1>.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q cntr_tri.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q col_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q demux_chip_sel_tri<3>.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q sel_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q sel_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q status_reg_data<0>.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_END.Q status_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q PRE.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q SAN_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q chip_sel<1>.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q cntr_tri.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q col_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q sel_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q sel_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.Q status_reg_data<1>.D 13.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/chip_read_5_1.D 13.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 13.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 13.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q PRE.D 13.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q SAN_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q chip_sel<1>.D 13.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q cntr_sel.D 13.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q cntr_set_value<0>.D 13.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q cntr_set_value<1>.D 13.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q cntr_set_value<2>.D 13.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q cntr_set_value<3>.D 13.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q cntr_set_value<5>.D 13.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q cntr_set_value<6>.D 13.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q cntr_tri.D 13.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q col_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q col_pulse.D 13.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q demux_chip_sel_tri<3>.D 13.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q sample_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q sel_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q sel_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q status_reg_data<1>.D 13.000
FSM/SHELL1_DSP_SM_2/cntr_rst.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 13.000
FSM/SHELL1_DSP_SM_2/cntr_rst.Q cntr_cnt<1>.D 13.000
FSM/SHELL1_DSP_SM_2/cntr_rst.Q cntr_cnt<2>.D 13.000
FSM/SHELL1_DSP_SM_2/cntr_rst.Q cntr_cnt<3>.D 13.000
FSM/SHELL1_DSP_SM_2/cntr_rst.Q cntr_cnt<4>.D 13.000
FSM/SHELL1_DSP_SM_2/cntr_rst.Q cntr_cnt<5>.D 13.000
FSM/SHELL1_DSP_SM_2/cntr_rst.Q cntr_cnt<6>.D 13.000
FSM/SHELL1_DSP_SM_2/cntr_rst.Q cntr_cnt<7>.D 13.000
FSM/SHELL1_DSP_SM_2/col_cnt0.Q FSM/SHELL1_DSP_SM_2/col_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/col_cnt0.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/col_cnt0.Q row_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/col_cnt0.Q row_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/col_cnt1.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/col_cnt1.Q row_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/col_cnt1.Q row_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/col_cnt2.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/col_cnt2.Q row_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/col_cnt2.Q row_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/col_cnt3.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/col_cnt3.Q row_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/col_cnt3.Q row_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/col_cnt4.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/col_cnt4.Q row_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/col_cnt4.Q row_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/col_cnt5.Q FSM/SHELL1_DSP_SM_2/col_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/col_cnt5.Q row_clk_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/col_cnt5.Q row_pulse_BUFR.D 13.000
FSM/SHELL1_DSP_SM_2/ramp_cnt1.Q FSM/SHELL1_DSP_SM_2/ramp_cnt1.D 13.000
FSM/SHELL1_DSP_SM_2/ramp_cnt3.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/ramp_cnt3.Q FSM/SHELL1_DSP_SM_2/ramp_cnt3.D 13.000
FSM/SHELL1_DSP_SM_2/ramp_cnt4.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/ramp_cnt5.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/ramp_cnt6.Q FSM/SHELL1_DSP_SM_2/ramp_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/ramps0.Q FSM/SHELL1_DSP_SM_2/ramps0.D 13.000
FSM/SHELL1_DSP_SM_2/ramps0.Q FSM/SHELL1_DSP_SM_2/ramps1.D 13.000
FSM/SHELL1_DSP_SM_2/ramps1.Q FSM/SHELL1_DSP_SM_2/ramps1.D 13.000
FSM/SHELL1_DSP_SM_2/row_cnt0.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 13.000
FSM/SHELL1_DSP_SM_2/row_cnt0.Q FSM/SHELL1_DSP_SM_2/row_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/row_cnt0.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 13.000
FSM/SHELL1_DSP_SM_2/row_cnt0.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/row_cnt0.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 13.000
FSM/SHELL1_DSP_SM_2/row_cnt1.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 13.000
FSM/SHELL1_DSP_SM_2/row_cnt1.Q FSM/SHELL1_DSP_SM_2/row_cnt1.D 13.000
FSM/SHELL1_DSP_SM_2/row_cnt1.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/row_cnt1.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 13.000
FSM/SHELL1_DSP_SM_2/row_cnt2.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 13.000
FSM/SHELL1_DSP_SM_2/row_cnt2.Q FSM/SHELL1_DSP_SM_2/row_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/row_cnt2.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 13.000
FSM/SHELL1_DSP_SM_2/row_cnt3.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 13.000
FSM/SHELL1_DSP_SM_2/row_cnt3.Q FSM/SHELL1_DSP_SM_2/row_cnt3.D 13.000
FSM/SHELL1_DSP_SM_2/sel_cnt0.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/sel_cnt0.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 13.000
FSM/SHELL1_DSP_SM_2/sel_cnt0.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/sel_cnt0.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 13.000
FSM/SHELL1_DSP_SM_2/sel_cnt1.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/sel_cnt1.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 13.000
FSM/SHELL1_DSP_SM_2/sel_cnt1.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/sel_cnt1.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 13.000
FSM/SHELL1_DSP_SM_2/sel_cnt2.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/sel_cnt2.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/sel_cnt2.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 13.000
FSM/SHELL1_DSP_SM_2/sel_cnt3.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/sel_cnt3.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/sel_cnt3.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 13.000
FSM/SHELL1_DSP_SM_2/tochip_command0.Q FSM/SHELL1_DSP_SM_2/CHIP_IDLE.D 13.000
FSM/SHELL1_DSP_SM_2/tochip_command0.Q FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.D 13.000
FSM/SHELL1_DSP_SM_2/tochip_command0.Q FSM/SHELL1_DSP_SM_2/chip_read_5_1.D 13.000
FSM/SHELL1_DSP_SM_2/tochip_command0.Q FSM/SHELL1_DSP_SM_2/cntr_rst.D 13.000
FSM/SHELL1_DSP_SM_2/tochip_command0.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/tochip_command0.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 13.000
FSM/SHELL1_DSP_SM_2/tochip_command0.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/tochip_command0.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 13.000
FSM/SHELL1_DSP_SM_2/tochip_command0.Q FSM/SHELL1_DSP_SM_2/tochip_command0.D 13.000
FSM/SHELL1_DSP_SM_2/tochip_command0.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 13.000
FSM/SHELL1_DSP_SM_2/tochip_command0.Q chip_sel<1>.D 13.000
FSM/SHELL1_DSP_SM_2/tochip_command0.Q status_reg_data<1>.D 13.000
FSM/SHELL1_DSP_SM_2/tochip_command0.Q status_reg_data<3>.D 13.000
FSM/SHELL1_DSP_SM_2/tochip_command0.Q status_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/tochip_command1.Q FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.D 13.000
FSM/SHELL1_DSP_SM_2/tochip_command1.Q FSM/SHELL1_DSP_SM_2/chip_read_5_1.D 13.000
FSM/SHELL1_DSP_SM_2/tochip_command1.Q FSM/SHELL1_DSP_SM_2/sel_cnt0.D 13.000
FSM/SHELL1_DSP_SM_2/tochip_command1.Q FSM/SHELL1_DSP_SM_2/sel_cnt1.D 13.000
FSM/SHELL1_DSP_SM_2/tochip_command1.Q FSM/SHELL1_DSP_SM_2/sel_cnt2.D 13.000
FSM/SHELL1_DSP_SM_2/tochip_command1.Q FSM/SHELL1_DSP_SM_2/sel_cnt3.D 13.000
FSM/SHELL1_DSP_SM_2/tochip_command1.Q FSM/SHELL1_DSP_SM_2/tochip_command1.D 13.000
FSM/SHELL1_DSP_SM_2/tochip_command1.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 13.000
FSM/SHELL1_DSP_SM_2/tochip_command1.Q chip_sel<1>.D 13.000
FSM/SHELL1_DSP_SM_2/tochip_command1.Q status_reg_data<1>.D 13.000
FSM/SHELL1_DSP_SM_2/tochip_command1.Q status_reg_data<3>.D 13.000
FSM/SHELL1_DSP_SM_2/tochip_command1.Q status_reg_load.D 13.000
FSM/SHELL1_DSP_SM_2/todsp_command0.Q FSM/SHELL1_DSP_SM_2/DONE_READ.D 13.000
FSM/SHELL1_DSP_SM_2/todsp_command0.Q FSM/SHELL1_DSP_SM_2/tochip_command1.D 13.000
FSM/SHELL1_DSP_SM_2/todsp_command0.Q FSM/SHELL1_DSP_SM_2/todsp_command0.D 13.000
FSM/SHELL1_DSP_SM_2/todsp_command1.Q FSM/SHELL1_DSP_SM_2/DONE_READ.D 13.000
FSM/SHELL1_DSP_SM_2/todsp_command1.Q FSM/SHELL1_DSP_SM_2/tochip_command1.D 13.000
FSM/SHELL1_DSP_SM_2/todsp_command1.Q FSM/SHELL1_DSP_SM_2/todsp_command1.D 13.000
PRE.Q PRE.D 13.000
SAN_BUFR.Q SAN_BUFR.D 13.000
SH_samp_0.Q SH_samp_0.D 13.000
chip_sel<1>.Q chip_sel<1>.D 13.000
cntr_8.Q cntr_8.D 13.000
cntr_9.Q cntr_9.D 13.000
cntr_cnt<0>.Q cntr_cnt<1>.D 13.000
cntr_cnt<0>.Q cntr_cnt<2>.D 13.000
cntr_cnt<0>.Q cntr_cnt<3>.D 13.000
cntr_cnt<0>.Q cntr_cnt<4>.D 13.000
cntr_cnt<0>.Q cntr_cnt<5>.D 13.000
cntr_cnt<0>.Q cntr_cnt<6>.D 13.000
cntr_cnt<0>.Q cntr_cnt<7>.D 13.000
cntr_cnt<1>.Q cntr_cnt<1>.D 13.000
cntr_cnt<1>.Q cntr_cnt<2>.D 13.000
cntr_cnt<1>.Q cntr_cnt<3>.D 13.000
cntr_cnt<1>.Q cntr_cnt<4>.D 13.000
cntr_cnt<1>.Q cntr_cnt<5>.D 13.000
cntr_cnt<1>.Q cntr_cnt<6>.D 13.000
cntr_cnt<1>.Q cntr_cnt<7>.D 13.000
cntr_cnt<2>.Q cntr_cnt<2>.D 13.000
cntr_cnt<2>.Q cntr_cnt<3>.D 13.000
cntr_cnt<2>.Q cntr_cnt<4>.D 13.000
cntr_cnt<2>.Q cntr_cnt<5>.D 13.000
cntr_cnt<2>.Q cntr_cnt<6>.D 13.000
cntr_cnt<2>.Q cntr_cnt<7>.D 13.000
cntr_cnt<3>.Q cntr_cnt<3>.D 13.000
cntr_cnt<3>.Q cntr_cnt<4>.D 13.000
cntr_cnt<3>.Q cntr_cnt<5>.D 13.000
cntr_cnt<3>.Q cntr_cnt<6>.D 13.000
cntr_cnt<3>.Q cntr_cnt<7>.D 13.000
cntr_cnt<4>.Q cntr_cnt<4>.D 13.000
cntr_cnt<4>.Q cntr_cnt<5>.D 13.000
cntr_cnt<4>.Q cntr_cnt<6>.D 13.000
cntr_cnt<4>.Q cntr_cnt<7>.D 13.000
cntr_cnt<5>.Q cntr_cnt<5>.D 13.000
cntr_cnt<5>.Q cntr_cnt<6>.D 13.000
cntr_cnt<5>.Q cntr_cnt<7>.D 13.000
cntr_cnt<6>.Q cntr_cnt<6>.D 13.000
cntr_cnt<6>.Q cntr_cnt<7>.D 13.000
cntr_cnt<7>.Q cntr_cnt<7>.D 13.000
cntr_sel.Q cntr_sel.D 13.000
cntr_set_value<0>.Q cntr_set_value<0>.D 13.000
cntr_set_value<1>.Q cntr_set_value<1>.D 13.000
cntr_set_value<2>.Q cntr_set_value<2>.D 13.000
cntr_set_value<3>.Q cntr_set_value<3>.D 13.000
cntr_set_value<5>.Q cntr_set_value<5>.D 13.000
cntr_set_value<6>.Q cntr_set_value<6>.D 13.000
cntr_tri.Q cntr_tri.D 13.000
col_clk_BUFR.Q col_clk_BUFR.D 13.000
col_pulse.Q col_pulse.D 13.000
comp_sleep.Q comp_sleep.D 13.000
dac_en.Q dac_en.D 13.000
demux_dsp_sel_load<0>.Q demux_dsp_sel_load<0>.D 13.000
demux_dsp_sel_load<1>.Q demux_dsp_sel_load<1>.D 13.000
demux_dsp_sel_load<2>.Q demux_dsp_sel_load<2>.D 13.000
demux_dsp_sel_load<3>.Q demux_dsp_sel_load<3>.D 13.000
demux_dsp_sel_tri<0>.Q demux_dsp_sel_tri<0>.D 13.000
demux_dsp_sel_tri<1>.Q demux_dsp_sel_tri<1>.D 13.000
demux_dsp_sel_tri<2>.Q demux_dsp_sel_tri<2>.D 13.000
demux_dsp_sel_tri<3>.Q demux_dsp_sel_tri<3>.D 13.000
post_sleep.Q post_sleep.D 13.000
pre_sleep_BUFR.Q pre_sleep_BUFR.D 13.000
row_clk_BUFR.Q row_clk_BUFR.D 13.000
row_pulse_BUFR.Q row_pulse_BUFR.D 13.000
sample_reg_load.Q sample_reg_load.D 13.000
sel_clk_BUFR.Q sel_clk_BUFR.D 13.000
sel_pulse_BUFR.Q sel_pulse_BUFR.D 13.000
status_reg_data<0>.Q status_reg_data<0>.D 13.000
status_reg_data<1>.Q status_reg_data<1>.D 13.000
status_reg_data<2>.Q status_reg_data<2>.D 13.000
status_reg_load.Q status_reg_load.D 13.000
transmit.Q transmit.D 13.000
FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.Q FSM/SHELL1_DSP_SM_2/PRE_RAMP.D 11.800
FSM/SHELL1_DSP_SM_2/CHIP_ADV_0.Q FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.D 11.800
FSM/SHELL1_DSP_SM_2/CHIP_IDLE.Q FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.D 11.800
FSM/SHELL1_DSP_SM_2/CHIP_READ2.Q FSM/SHELL1_DSP_SM_2/CHIP_READ3.D 11.800
FSM/SHELL1_DSP_SM_2/CHIP_READ3.Q FSM/SHELL1_DSP_SM_2/CHIP_READ4.D 11.800
FSM/SHELL1_DSP_SM_2/CHIP_READ4.Q FSM/SHELL1_DSP_SM_2/CHIP_READ_5.D 11.800
FSM/SHELL1_DSP_SM_2/CHIP_READ_0.Q FSM/SHELL1_DSP_SM_2/CHIP_READ_1.D 11.800
FSM/SHELL1_DSP_SM_2/CHIP_SAMPLE0_1.Q FSM/SHELL1_DSP_SM_2/CHIP_ACQUIRE.D 11.800
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/XMIT_END.D 11.800
FSM/SHELL1_DSP_SM_2/CHIP_TRANSMIT.Q FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.D 11.800
FSM/SHELL1_DSP_SM_2/CLR_0.Q FSM/SHELL1_DSP_SM_2/CLR_0_1.D 11.800
FSM/SHELL1_DSP_SM_2/CLR_0_1.Q FSM/SHELL1_DSP_SM_2/CLR_1.D 11.800
FSM/SHELL1_DSP_SM_2/CLR_1.Q FSM/SHELL1_DSP_SM_2/CLR_1_1.D 11.800
FSM/SHELL1_DSP_SM_2/CLR_1_1.Q FSM/SHELL1_DSP_SM_2/CLR_2.D 11.800
FSM/SHELL1_DSP_SM_2/CLR_2.Q FSM/SHELL1_DSP_SM_2/CLR_2_1.D 11.800
FSM/SHELL1_DSP_SM_2/IDLE.Q FSM/SHELL1_DSP_SM_2/DSP_READ.D 11.800
FSM/SHELL1_DSP_SM_2/IDLE.Q FSM/SHELL1_DSP_SM_2/WRITE_STATUS.D 11.800
FSM/SHELL1_DSP_SM_2/IDLE.Q FSM/SHELL1_DSP_SM_2/WRITE_XMIT.D 11.800
FSM/SHELL1_DSP_SM_2/PRE_READ.Q FSM/SHELL1_DSP_SM_2/PRE_READ_1.D 11.800
FSM/SHELL1_DSP_SM_2/PRE_READ.Q cntr_set_value<7>.D 11.800
FSM/SHELL1_DSP_SM_2/PRE_READ_1.Q FSM/SHELL1_DSP_SM_2/CHIP_READ_0.D 11.800
FSM/SHELL1_DSP_SM_2/RAMP_S1.Q FSM/SHELL1_DSP_SM_2/RAMP_S2.D 11.800
FSM/SHELL1_DSP_SM_2/RAMP_S2.Q FSM/SHELL1_DSP_SM_2/RAMP_S3.D 11.800
FSM/SHELL1_DSP_SM_2/chip_read_5_1.Q FSM/SHELL1_DSP_SM_2/CHIP_READ_6.D 11.800
FSM/SHELL1_DSP_SM_2/cntr_rst.Q cntr_cnt<0>.D 11.800
FSM/SHELL1_DSP_SM_2/col_cnt0.Q FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.D 11.800
FSM/SHELL1_DSP_SM_2/col_cnt0.Q FSM/SHELL1_DSP_SM_2/CLR_2.D 11.800
FSM/SHELL1_DSP_SM_2/col_cnt1.Q FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.D 11.800
FSM/SHELL1_DSP_SM_2/col_cnt1.Q FSM/SHELL1_DSP_SM_2/CLR_2.D 11.800
FSM/SHELL1_DSP_SM_2/col_cnt2.Q FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.D 11.800
FSM/SHELL1_DSP_SM_2/col_cnt2.Q FSM/SHELL1_DSP_SM_2/CLR_2.D 11.800
FSM/SHELL1_DSP_SM_2/col_cnt3.Q FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.D 11.800
FSM/SHELL1_DSP_SM_2/col_cnt3.Q FSM/SHELL1_DSP_SM_2/CLR_2.D 11.800
FSM/SHELL1_DSP_SM_2/col_cnt4.Q FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.D 11.800
FSM/SHELL1_DSP_SM_2/col_cnt4.Q FSM/SHELL1_DSP_SM_2/CLR_2.D 11.800
FSM/SHELL1_DSP_SM_2/col_cnt5.Q FSM/SHELL1_DSP_SM_2/CHIP_ADV_1.D 11.800
FSM/SHELL1_DSP_SM_2/col_cnt5.Q FSM/SHELL1_DSP_SM_2/CLR_2.D 11.800
FSM/SHELL1_DSP_SM_2/sel_cnt0.Q FSM/SHELL1_DSP_SM_2/CLR_1.D 11.800
FSM/SHELL1_DSP_SM_2/sel_cnt1.Q FSM/SHELL1_DSP_SM_2/CLR_1.D 11.800
FSM/SHELL1_DSP_SM_2/sel_cnt2.Q FSM/SHELL1_DSP_SM_2/CLR_1.D 11.800
FSM/SHELL1_DSP_SM_2/sel_cnt3.Q FSM/SHELL1_DSP_SM_2/CLR_1.D 11.800
FSM/SHELL1_DSP_SM_2/tochip_command0.Q FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.D 11.800
FSM/SHELL1_DSP_SM_2/tochip_command0.Q FSM/SHELL1_DSP_SM_2/CHIP_READ_6.D 11.800
FSM/SHELL1_DSP_SM_2/tochip_command1.Q FSM/SHELL1_DSP_SM_2/CHIP_LOAD_STATUS.D 11.800
FSM/SHELL1_DSP_SM_2/tochip_command1.Q FSM/SHELL1_DSP_SM_2/CHIP_READ_6.D 11.800
cntr_cnt<0>.Q FSM/SHELL1_DSP_SM_2/XMIT_END.D 11.800
cntr_cnt<0>.Q FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.D 11.800
cntr_cnt<0>.Q cntr_cnt<0>.D 11.800
cntr_cnt<1>.Q FSM/SHELL1_DSP_SM_2/XMIT_END.D 11.800
cntr_cnt<1>.Q FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.D 11.800
cntr_cnt<2>.Q FSM/SHELL1_DSP_SM_2/XMIT_END.D 11.800
cntr_cnt<2>.Q FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.D 11.800
cntr_cnt<3>.Q FSM/SHELL1_DSP_SM_2/XMIT_END.D 11.800
cntr_cnt<3>.Q FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.D 11.800
cntr_cnt<4>.Q FSM/SHELL1_DSP_SM_2/XMIT_END.D 11.800
cntr_cnt<4>.Q FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.D 11.800
cntr_cnt<5>.Q FSM/SHELL1_DSP_SM_2/XMIT_END.D 11.800
cntr_cnt<5>.Q FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.D 11.800
cntr_cnt<6>.Q FSM/SHELL1_DSP_SM_2/XMIT_END.D 11.800
cntr_cnt<6>.Q FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.D 11.800
cntr_cnt<7>.Q FSM/SHELL1_DSP_SM_2/XMIT_END.D 11.800
cntr_cnt<7>.Q FSM/SHELL1_DSP_SM_2/XMIT_SLEEP.D 11.800


Pad to Pad List

Source Pad Destination Pad Delay
data<10> dsp_data<10> 12.800
data<11> dsp_data<11> 12.800
data<12> dsp_data<12> 12.800
data<13> dsp_data<13> 12.800
data<14> dsp_data<14> 12.800
data<15> dsp_data<15> 12.800
data<16> dsp_data<16> 12.800
data<17> dsp_data<17> 12.800
data<18> dsp_data<18> 12.800
data<19> dsp_data<19> 12.800
data<20> dsp_data<20> 12.800
data<21> dsp_data<21> 12.800
data<22> dsp_data<22> 12.800
data<23> dsp_data<23> 12.800
data<24> dsp_data<24> 12.800
data<25> dsp_data<25> 12.800
data<26> dsp_data<26> 12.800
data<27> dsp_data<27> 12.800
data<28> dsp_data<28> 12.800
data<29> dsp_data<29> 12.800
data<30> dsp_data<30> 12.800
data<31> dsp_data<31> 12.800
data<8> dsp_data<8> 12.800
data<9> dsp_data<9> 12.800
CLK dac_clk 10.800


Number of paths analyzed: 3758
Number of Timing errors: 3758
Analysis Completed: Mon Jun 12 16:13:52 2006